1. Field of the Invention
The present invention relates to a method for manufacturing a thin film transistor (TFT) panel.
2. Description of the Related Art
In order to minimize the space required by display devices, researches have been undertaken into the development of various flat panel display devices such as LCD display devices, plasma display panels (PDP) and electro-luminescence displays (EL). Particularly, in the case of LCD display devices, liquid crystal technology has been explored because the optical characteristics of liquid crystal material can be controlled in response to changes in electric fields applied thereto.
At present, the dominant methods for fabricating liquid crystal display devices (LCD) and panels are methods based on amorphous silicon (a-Si) thin film transistor (TFT) technologies. Using these technologies, high quality image displays of substantial size can be fabricated by using low temperature processes. As will be understood by those skilled in the art, conventional LCD devices typically include a TFT panel, a color filter panel and a liquid crystal layer interposed therebetween.
FIG. 1 is a flowchart illustrating the steps of a conventional method of forming a TFT panel, and FIGS. 2a-2e are sectional views illustrating a portion of a TFT panel manufactured by the conventional method of FIG. 1.
A conventional method for manufacturing a TFT panel will now be described with reference to FIGS. 1 and 2a-2c. First, a first metal layer is sputtered on a transparent glass substrate 200 to a predetermined thickness (step 101). In FIG. 2a, the first metal layer is etched by a first photolithography process to form a gate electrode 202 and a gate line (not shown) on the substrate 200 (step 102). Then, an insulating layer (e.g., SiN, layer) is deposited on the entire surface of the substrate having the gate electrode 202 and the gate line (not shown) thereon to form a gate insulating layer 204. An amorphous silicon layer 206 and an impurity-doped amorphous silicon layer 208 (e.g., n+ amorphous silicon layer), are then sequentially deposited on the gate insulating layer 204 to form an amorphous semiconductor layer 210 (step 103). Next, as shown in FIG. 2b, the amorphous semiconductor layer 210 is patterned by a second photolithography process with a photoresist pattern 211 with substantially uniform thickness, resulting in an amorphous semiconductor pattern 212 on the TFT portion of the substrate 200 (step 104).
Then, a second metal layer such as Cr is sputtered on the entire surface of the gate insulating layer 204 and on the amorphous semiconductor pattern 212 to a predetermined thickness (step 105). As shown in FIG. 2c, the second metal layer is then patterned by a third photolithography process using a photoresist pattern 220 to form a data line (not shown), a source electrode 216 and a drain electrode 214 on the TFT portion of the substrate, wherein the source electrode 216 and the drain electrode 214 are separated by a channel portion 218 (step 106).
In FIG. 2d, the impurity-doped amorphous silicon layer 208 at the channel region 218 is etched by using the source and drain electrodes 216 and 214 as an etch-protect mask (step 107). Then, as shown in FIG. 2e, the photoresist pattern 220 is removed.
A passivation layer (not shown, e.g., SiNx layer) is then formed on the entire surface of the above structure to a predetermined thickness (step 108). The passivation layer is then patterned to expose parts of the drain electrode 214 using a fourth photolithography process (step 109). After forming an indium-tin-oxide (ITO) layer as a transparent conductive layer on the entire surface of the structure having the passivation layer pattern thereon (step 110), the ITO layer is patterned by a fifth photolithography process (step 111).
The steps 104 and 107 described above can be conducted by an etching equipment of the same type, but the intervening steps 105 and 106 are conducted by equipments different from the etching equipment used in the steps 104 and 107. Therefore, the etched product of the step 104 must be transported out of the etching equipment to the processing equipments of the steps 105 and 106, and then the processed product of the step 106 is transported back to the etching equipment for performing the step 107. It is desirable to perform the steps 104 and 107 sequentially because of the cost and lengthy time required for the additional transportation described above. Furthermore, the etching process of the step 107 may cause corrosion of the second metal pattern.
The present invention therefore seeks to provide an improved method for manufacturing a TFT panel that overcomes, or at least reduces the above-mentioned problems of the prior art.
It is an object of the present invention to provide a method for manufacturing a TFT panel which allows the patterning processes of the semiconductor layer and the impurity-doped layer to be conducted sequentially thereby reducing the manufacturing cost and increasing the productivity.
It is another object of the present invention to provide a method for manufacturing a TFT panel which resolves the above-mentioned corrosion issue of the second metal pattern.
In the manufacturing method of a thin film transistor panel of the present invention, a first metal pattern including at least a gate line with a gate electrode is formed on an insulating substrate such as a transparent glass substrate. Next, a gate insulating layer is deposited over the gate line. A semiconductor layer which comprises an amorphous silicon layer and an impurity-doped layer, e.g., an n+ amorphous silicon layer, is formed on the gate insulating layer.
Thereafter, a photoresist pattern is formed on the semiconductor layer. The photoresist pattern includes a first portion facing a channel region, a second portion that is thicker than the first portion, and a third portion having no photoresist. The semiconductor layer is etched by using the photoresist pattern as an etch mask to expose the gate insulating layer under the third portion of the photoresist pattern. Then, the thickness of the photoresist pattern layer is reduced, for example, by O2 ashing, until the first portion of the photoresist.pattern is removed so as to expose the impurity-doped layer at the channel region. Then, the impurity-doped layer exposed at the channel region is removed by etching. Finally, a conductive pattern layer with source and drain electrodes, i.e., the second metal pattern, is formed over the patterned semiconductor layer and the gate insulating layer, wherein the drain and source electrodes are separated by the channel region.
According to a preferred embodiment of the present invention, the photoresist pattern is provided by the following steps. First, a photoresist film is formed on the semiconductor layer. Next, a mask with a predetermined pattern having at least a slit is placed on top of the photoresist film and the photoresist film is exposed to a light. Finally, the exposed photoresist film is developed to obtain the photoresist pattern with the thinner first portion formed corresponding to the slit of the mask.
In the manufacturing method of a thin film transistor panel of the present invention, the patterning processes of the semiconductor layer and the impurity-doped layer are performed sequentially. Therefore, the patterning steps described above can be conducted by the same etching equipment so as to skip the additional transportation between different equipments thereby reducing the manufacturing cost and increasing the productivity.
Furthermore, the impurity-doped layer is patterned before forming the second metal pattern so as to prevent the second metal pattern from being corroded by the etchant used in the patterning process thereby resolving the corrosion issue described above.